The present invention relates to a computer into which a number of assists can be easily added without compromising software compatibility. An assist is hardware which extends a processor's capability. The proposed computer can support assists that are undefined at the computer's date of design. In addition to being able to execute a basic instruction set, the computer can execute one or more extension instruction sets. An extension instruction set contains instructions that do not belong to the basic instruction set. The computer can implement the extension instruction, either executed in hardware via an assist, or emulated in software via a trap.
In the prior art, it was either impossible or impractical to incorporate an assist into a computer, if the assist was undefined at the computer's date of design. Incorporating the assist into the computer would adversely impact datapaths and controls of a processor within the ccmputer, and would fail to satisfy speed requirements for both a main processor and the assist. Another version of the computer would have to be designed which could more practically incorporate the assist.
In the prior art, a computer sometimes incorporated a floating-point accelerator as a very specialized add-on assist. A typical floating-point accelerator had a highly specialized interface to a processor. This highly specialized interface did not allow an incorporation of a different type of assist.
In the prior art, a limited method was devised whereby only a very few assists could be added to a computer. Software programs written for a first computer, the first computer including a first main processor and a first assist, were not portable to a second computer, the second computer including the first main processor but not the first assist.
In the prior art, a first computer was designed to execute a basic instruction set. The first computer suffered the disadvantage of being unable to execute extension instructions defined at a later date. A second computer had to be designed which could execute the extension instructions as well as the basic instruction set. There was no upward compatibility; although the second computer could execute programs written for the first computer, the first computer could not execute programs written for the second computer.
In the prior art, a scheme was devised whereby numerous opcodes were reserved within a basic instruction set for extension instructions. The scheme was less than optimal, since too much valuable opcode space in the basic instruction set was reserved for currently undefined extension instructions.
In a variation of the scheme just discussed, a second scheme was devised in which minimal opcode space in the basic instruction set was reserved for an escape instruction. The escape instruction indicated that subsequent instructions were not to be decoded as part of the basic set, but as extension instructions, until another escape instruction was encountered. While the second scheme solved a disadvantage in which too many opcodes were reserved for extension instructions, the first computer was still unable to execute an extension instruction, and a second computer had to be designed.
In the prior art, a computer was designed to run with an add-on assist either present or absent. If the add-on assist was present in a configuration, a program with an extension instruction intended for the add-on assist would be executed in hardware by the add-on assist. If the add-on assist was absent in the configuration, code had to be written with a branch instruction instead of the extension instruction. The branch instruction caused execution to jump to a software routine that would emulate execution of the extension instruction.
A serious disadvantage of the branch instruction was that it did not provide software compatiblity. Code written for a first computer that incorporated the add-on assist was not portable to a second computer that did not incorporate the add-on assist, unless the code was completely recompiled. Code written for the second computer had to be completely recompiled if the code was to operate efficiently as possible on the first computer.
Another disadvantage of the branch instruction was that it did not provide fault tolerance at run-time. No option for emulation existed at run-time if the add-on assist failed. If the add-on assist failed at run-time, code written for the first computer could not be executed.